Publications

In Journals

1. VLSI ARCHITECTURE FOR PARALLEL MULTIPLIERS , INTERNATIONAL JOURNAL OF SCIENCE AND INNOVATIVE ENGINEERING & TECHNOLOGY,MAY 2017 , ISSUE VOLUME 4, ISBN 978-81-904760-9-6.
2. Performance Comparison of Weighted Modulo (2ⁿ +1) Adder using Different Prefix Structures , International Journal of Electronics, Electrical and Computational System,IJEECS,ISSN 2348-117X ,Volume 6, Issue 8,August 201
3. Power-Efficient Carry Select Adder, International Journal of Research e-ISSN: 2348-6848 p-ISSN: 2348-795X Volume 04 Issue14 November 2017
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At Conferences

1.     VLSI ARCHITECTURE FOR PARALLEL MULTIPLIERS ,7^th international conference on recent engineering & technology, ORGANIZATION OF SCIENCE & INNOVATIVE ENGINEERING AND TECHNOLOGY, CHENNAI , IN ASSOCIATION WITH MATRUSRI ENGINEERING COLLEGE, HYDERABAD
2.     Performance Comparison of Weighted Modulo (2ⁿ +1) Adder using Different Prefix Structures, 6th International Conference on Research Trends in Engineering, Applied Science and Management (ICRTESM-2017) at Institution Of Electronics and Telecommunication Engineers,1st Cross Road, Bellary Road, Ganganagar,Bengaluru, Karnataka, India on 6th August 2017, ISBN: 978-81-934288-0-1.
3.    EFFECTIVE FOOD GRAIN LOSS REDUCTION TECHNIQUE USING IOT, 2017 IJCRT | National Conference Proceeding NTSET Feb 2018 | ISSN: 2320-2882 National Conference On Trends In Science, Engineering & Technology by Matrusri Engineering College & IJCRT , IJCRTNTSE010 International Journal of Creative Research Thoughts (IJCRT) www.ijcrt.org